Embodiments of the invention relate generally to structures and methods for packaging semiconductor devices and, more particularly, to a power overlay (POL) packaging structure that includes an improved thermal interface.
Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronic circuits, such as switched mode power supplies, for example. Most power semiconductor devices are only used in commutation mode (i.e., they are either on or off), and are therefore optimized for this. Many power semiconductor devices are used in high voltage power applications and are designed to carry a large amount of current and support a large voltage. In use, high voltage power semiconductor devices are connected to an external circuit by way of a power overlay (POL) packaging and interconnect system.
The general structure of a prior art power overlay (POL) structure 10 is shown in FIG. 1. The standard manufacturing process for the POL structure 10 typically begins with placement of one or more power semiconductor devices 12 onto a dielectric layer 14 by way of an adhesive 16. Metal interconnects 18 (e.g., copper interconnects) are then electroplated onto dielectric layer 14 to form a direct metallic connection to the power semiconductor devices 12. The metal interconnects 18 may be in the form of a low profile (e.g., less than 200 micrometers thick), planar interconnect structure that provides for formation of an input/output (I/O) system 20 to and from the power semiconductor devices 12. For connecting to an external circuit, such as by making a second level interconnection to a printed circuit board for example, current POL packages use solder ball grid arrays (BGAs) or land grid arrays (LGAs).
A heat sink 22 is also typically included in the POL structure 10 to providing a way to remove the heat generated by semiconductor devices 12 and protect the devices 12 from the external environment. Heat sink 22 is thermally coupled to the devices 12 using a direct bond copper (DBC) substrate 24. As shown, DBC substrate 24 is positioned between the upper surfaces of semiconductor devices 12 and the lower surface of heat sink 22.
DBC substrate 24 is a prefabricated component that includes a non-organic ceramic substrate 26 such as, for example, alumina, with upper and lower sheets of copper 28, 30 bonded to both sides thereof via a direct bond copper interface or braze layer 31. The lower copper sheet 30 of DBC substrate 24 is patterned to form a number of conductive contact areas before DBC substrate 24 is attached to semiconductor devices 12. A typically DBC substrate may have an overall thickness of approximately 1 mm.
During the fabrication process of POL structure 10, solder 32 is applied to the surfaces of semiconductor devices 12. DBC substrate 24 is then lowered onto solder 32 to align the patterned portions of lower copper sheet 30 with solder 32. After DBC substrate 24 is coupled to semiconductor devices 12, an underfill technique is used to apply a dielectric organic material 34 in the space between adhesive layer 16 and DBC substrate 24 to form a POL sub-module 36. A thermal pad or thermal grease 38 is then applied to the upper copper layer 28 of DBC substrate 24.
The use of a DBC substrate in a POL structure 10 has a number of limitations. First, the material properties of the copper and ceramic materials of the DBC substrate place inherent limitations on the design of the DBC substrate. For example, due to the inherent stiffness of ceramics and the differences in the thermal expansion coefficients of the copper and ceramic materials of DBC substrate 24, copper sheets 28, 30 must be kept relatively thin to avoid undue stresses placed on the ceramics caused by large swings in temperature in the copper material. In addition, since the surface of the lower copper layer of the DBC substrate 24 that faces semiconductor device(s) 12 is planar, the DBC substrate 24 does not facilitate fabrication of a POL package having semiconductor devices of differing height.
Also, DBC substrates are relatively expensive to manufacture and are a prefabricated component. As DBC substrate 24 is a prefabricated component, the thickness of copper sheets 28, 30 is predetermined based on the thickness of the copper foil layer applied to the ceramic substrate 26. Also, because DBC substrate 24 is fabricated prior to assembly with the remainder of the components of the POL structure, the dielectric filler or epoxy substrate that surrounds the semiconductor devices 12 is applied using an underfill technique after the DBC substrate 24 is coupled to semiconductor devices 12. This underfill technique is time consuming and can result in undesirable voids within the POL structure.
Therefore, it would be desirable to provide a POL structure having an improved thermal interface that overcomes the aforementioned structural and processing limitations of known POL structures that incorporate a DBC substrate. It would further be desirable for such a POL structure to account for semiconductor devices of different thickness while minimizing cost of the POL structure.